Analog & Mixed-Signal Design
About the role
This role involves designing and integrating clock generation and distribution circuits to maintain alignment across parallel lanes in high-speed optical links. Focus areas span PLL integration, clock receivers, phase alignment, and low-jitter distribution from specification through silicon.
What you'll do
- Design and integrate clocking circuits including PLLs, clock receivers, buffers, phase interpolators or DLLs, duty-cycle correction, and phase alignment.
- Design low-jitter clock distribution networks across parallel lanes.
- Analyze jitter and phase noise, and maintain the jitter budget with the clocking lead and system architect.
- Evaluate licensed PLL IP against requirements and support its integration.
- Analyze supply sensitivity and coupling, and collaborate with layout engineers on clock routing and shielding.
- Deliver behavioral models for system verification and correlate them with transistor-level results and silicon measurements.
What you'll need
- MS in Electrical Engineering (or BS with equivalent experience) and 5+ years of clocking circuit design experience.
- Tape-out experience with PLL, DLL, phase interpolator, or CDR circuits.
- Experience performing jitter and phase-noise analysis using tools such as Spectre RF (PSS/pnoise).
- Circuit design experience in FinFET or other advanced CMOS processes.
- Post-layout extraction and signoff experience.
Nice to have
- Experience with forwarded-clock or source-synchronous parallel interfaces.
- Experience with clock distribution for multi-lane I/O.
- Integration experience with third-party PLL IP.
- Jitter modeling experience in MATLAB or Python.
- Hands-on lab jitter and phase-noise measurement experience.
- 10+ years of experience with technical leadership of clocking designs through production.
Skills: PLL, jitter, phase noise, DLL, Spectre RF, clock distribution
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