Senior Principal Analog Methodology Engineer
$204,000 - $306,000 USD yearly
About the role
As a Senior Principal Analog Methodology Engineer, you will define and optimize the analog and mixed-signal design ecosystem, focusing on CAD tool flows, Cadence Virtuoso design environments, and Process Design Kit (PDK) integrations.
What you'll do
- Develop, maintain, and automate analog design flows covering schematic capture, simulation, and verification processes including DRC, LVS, PEX, and EM/IR analysis.
- Integrate and validate foundry Process Design Kits (PDKs) tailored to specific technology nodes.
- Create and maintain scripts using SKILL, Python, and Perl to improve efficiency and minimize rework.
- Collaborate with vendors and internal teams to evaluate, benchmark, and integrate EDA tools into the design ecosystem.
- Manage Linux-based design environments, including LSF compute farms and license servers.
- Oversee design data governance by managing large-scale analog libraries, hierarchical structures, and technology files.
What you'll need
- Bachelor's degree in Electrical or Computer Engineering with 12+ years of experience, a Master's degree with 8+ years, or a PhD with 5+ years.
- Proven experience in analog design and layout methodology, along with EDA tool support.
- Strong expertise with Cadence Virtuoso/Custom Compiler, SPICE/Spectre simulators, Virtuoso ADE simulation tool suite, and layout verification tools.
- High proficiency in scripting with SKILL, shell programming, and Python for automation solutions.
- Hands-on experience working with foundry PDKs at advanced technology nodes.
Skills: Cadence Virtuoso, PDK integration, analog design flows, DRC LVS PEX, SKILL Python Perl
More semiconductor jobs: EDA tools engineer jobs · Santa Clara jobs
This role has been open 89 days — well above the 67-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
731
|
Median days open
67 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (731 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 731 |
| Open roles in the wider Physical Implementation family | 10 | 1606 · 116 employers |
| Median days open | 89 d | 67 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Cadence Virtuoso, PDK integration, analog design flows, DRC LVS PEX, SKILL Python Perl
Who's hiring in this category
- Cadence Design Systems · 162 open roles · median 163 d
- Synopsys · 61 open roles · median 54 d
- Micron Technology · 48 open roles · median 45 d
- NVIDIA · 44 open roles · median 103 d
- Renesas Electronics · 41 open roles · median 16 d
- Keysight Technologies · 33 open roles · median 117 d
How we counted: 731 open EDA/CAD Engineering (EDA Tools) roles from 77 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.