Senior Principal AI Interconnect Architect
$202,200 - $343,700 USD yearly
Architecture role focused on PCIe, CXL, UALink, and Ultra Ethernet for AI inference infrastructure.
Originally posted 4 August 2026 by the employer.
About the role
The Senior Principal AI Interconnect Architect defines and engineers high-speed networking and communication systems across servers, racks, and chips for AI Inference infrastructure. The role focuses on bandwidth, power efficiency, scalability, and transport protocols incorporating PCIe, CXL, co-packaged optics, UALink, and Ultra Ethernet.
What you'll do
- Develop architectures for chip-to-chip interconnects and switched fabrics tailored for AI/ML scale-out.
- Analyze trade-offs in bandwidth, latency, power, area, and reliability.
- Participate in industry standard bodies and contribute to the direction of industry specifications.
- Work with SoC, package design, and software teams to ensure seamless integration.
What you'll need
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
- 10 - 15 years experience developing interconnect technologies including transport and link level protocols, switching fabrics, QoS and reliable communication methods, and Software Defined Networking.
- Familiarity with fabric topologies including Fat tree, Leaf-Spine (Clos), Torus, and Meshed, and their applicability to workload and system configurations.
- Familiarity with AI Hardware Architecture, GPU/accelerator clusters, and data center infrastructure.
- Deep, working knowledge of interconnect technologies and protocols such as PCIe, CXL, NVLink, UALink, Ethernet, Ultra-Ethernet, and serial links.
- Ability to develop performance models for modeling and simulation.
Skills: chip-to-chip interconnect, switching fabrics, PCIe, CXL, NVLink, performance modeling
More semiconductor jobs: SanDisk jobs · SoC design jobs · California jobs
This role has been open 0 days — well below the 74-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
468
|
Median days open
74 d
|
Category median salary (all employers)
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (468 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 468 |
| Open roles in the wider Digital Design & Verification family | 26 | 3333 · 115 employers |
| Median days open | 0 d | 74 d (−74 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: chip-to-chip interconnect, switching fabrics, PCIe, CXL, NVLink, performance modeling
Who's hiring in this category
- Qualcomm · 77 open roles · median 84 d
- NVIDIA · 54 open roles · median 71 d
- Apple · 44 open roles · median 21 d
- AMD · 40 open roles · median 62 d
- Arm Holdings · 30 open roles · median 2 d
- Micron Technology · 21 open roles · median 106 d
How we counted: 468 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.