Senior Power Integrity Engineer - LPU Packaging - CA, Santa Clara, United States
Originally posted 24 July 2026 by the employer — open 48 days.
Join the LPU Packaging team.
About the role
This role involves defining and optimizing power delivery from die/package through board, tray, and rack levels for the full product development cycle. The position focuses on power integrity for GPU, HBM, and high-speed SerDes products within advanced packaging integrations.
What you'll do
- Define best-in-class power delivery design and optimization practices from die/package through board, tray, and rack levels.
- Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response.
- Architect package-level PDNs by collaborating on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations.
- Drive system-level PI design, including board-level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams.
- Perform PI extraction and simulation for advanced packages and develop integrated chip–package–board co‑simulation flows using industry-standard tools.
- Generate and deploy reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partners.
- Define and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications.
- Debug complex system-level issues including rail noise, jitter‑induced errors, resets, and margin loss during hardware testing and validation.
What you'll need
- MS or PhD in Electrical Engineering or a related field, or equivalent experience.
- 12+ years of relevant work experience in Power Integrity.
- Strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs.
- Proven ownership of the chip-package-board PDN design and sign-off process.
- Hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages.
- Direct experience in the co-design of bump/ball maps, power/ground planes, and decoupling capacitor networks.
- Proficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools (eg, PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, or SPICE).
- Deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards.
- Experience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to correlate measured noise and droop to original specifications.
Skills: power integrity, power delivery design, PDN targets, package-level PDN architect, chip–package–board co‑simulation, PI extraction and simulation
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 217 |
| Median days open | 95 d | 91 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: power integrity, power delivery design, PDN targets, package-level PDN architect, chip–package–board co‑simulation, PI extraction and simulation
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA (this employer) · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.