Senior Post-Silicon PCIe Characterization Engineer - Chandler, Arizona, United States
$161,500 - $218,500 USD yearly
Originally posted 11 September 2026 by the employer.
About the role
As a Senior Post-Silicon PCIe Characterization Engineer, you will focus on PCIe interfaces, characterizing silicon across process, voltage, temperature, and frequency conditions. You will collaborate across engineering teams to analyze results, debug issues, and improve silicon performance on Arm SoCs.
What you'll do
- Develop and enable system-level stress workloads on Linux and Bare-Metal SW environments. - Collaborate with the post-silicon validation team to leverage test content to characterize silicon at the system level. - Debug and resolve system issues and bugs using protocol analyzers, scopes, debuggers, or similar tools. - Develop test plans and implement tests for characterizing silicon at the system level. - Analyze data to evaluate voltage/frequency margining and silicon operating limits.
What you'll need
- Experience in pre- or post-silicon validation and characterization, with an understanding of silicon power, performance, and PVT behavior. - Experience with PCIe architecture, including link initialization, training, equalization, and PHY operation. - Software skills including C/C++, Arm assembly, Python, or scripting languages. - Experience with voltage/frequency margining and silicon operating limits. - Experience debugging PCIe, silicon, and system issues using protocol analyzers, scopes, debuggers, or similar tools. - Ability to analyze data, tackle sophisticated problems, and communicate technical findings.
Nice to have
- Experience with PCIe PHY characterization, link behavior, signal integrity, and protocol-level debug, including PCIe Gen4, Gen5, Gen6, or related high-speed interfaces. - Experience characterizing PCIe performance, stability, operating margins, and failure behavior. - Experience with PCIe protocol analysis, error handling, link recovery, or compliance testing. - Experience developing Python automation for characterization and data analysis. - Experience with Arm-based SoCs, CPUs, PCIe controllers, or high-speed interfaces. - Understanding of system-level testing and correlation with manufacturing test.
This role has been open 0 days — well below the 76-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
114
|
Median days open
76 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (114 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 114 |
| Open roles in the wider Silicon Validation & Test family | 21 | 2320 · 114 employers |
| Median days open | 0 d | 76 d (−76 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 43 d
- AMD · 16 open roles · median 76 d
- NVIDIA · 12 open roles · median 79 d
- Graphcore · 10 open roles · median 133 d
- Altera · 5 open roles · median 69 d
- Micron Technology · 5 open roles · median 223 d
How we counted: 114 open Post-Silicon Validation (Design Verification) roles from 31 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.