Senior Post-Silicon DDR Characterization Engineer - Chandler, Arizona, United States
$161,500 - $218,500 USD yearly
Originally posted 11 September 2026 by the employer.
Characterize DDR/LPDDR memory subsystems across process, voltage, temperature, and frequency conditions on Arm SoCs.
About the role
As a Senior Post-Silicon DDR Characterization Engineer, you will focus on DDR/LPDDR memory subsystems, characterizing silicon across process, voltage, temperature, and frequency conditions. You will collaborate across engineering teams to analyze results, debug issues, and improve silicon performance.
What you'll do
- Develop and enable system-level stress workloads on Linux and bare-metal software environments. - Collaborate with the post-silicon validation team to leverage test content to characterize silicon at the system level. - Debug and resolve system issues and bugs. - Develop test plans and implement tests for characterizing silicon at the system level.
What you'll need
- Experience in pre- or post-silicon validation and characterization, with an understanding of silicon power, performance, and PVT behavior. - Experience with DDR/LPDDR architectures, including training, calibration, timing, and PHY operation. - Software skills including C/C++, Arm assembly, Python, or scripting languages. - Experience with voltage/frequency margining and silicon operating limits. - Experience debugging silicon and system issues using scopes, logic analyzers, debuggers, or similar tools. - Ability to analyze data, solve complex problems, and communicate technical findings.
Nice to have
- Experience with DDR/LPDDR PHY characterization, memory-controller interactions, and LPDDR4/4X, LPDDR5/5X, DDR4, DDR5, or related technologies. - Experience characterizing memory performance, stability, operating margins, and failure behavior. - Experience developing Python automation for characterization and data analysis. - Experience with low-level C, firmware, hardware control, or silicon debug. - Experience with Arm-based SoCs, CPUs, or memory subsystems. - Understanding of system-level testing and correlation with manufacturing test.
This role has been open 0 days — well below the 76-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
114
|
Median days open
76 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (114 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 114 |
| Open roles in the wider Silicon Validation & Test family | 21 | 2320 · 114 employers |
| Median days open | 0 d | 76 d (−76 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 43 d
- AMD · 16 open roles · median 76 d
- NVIDIA · 12 open roles · median 79 d
- Graphcore · 10 open roles · median 133 d
- Altera · 5 open roles · median 69 d
- Micron Technology · 5 open roles · median 223 d
How we counted: 114 open Post-Silicon Validation (Design Verification) roles from 31 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.