Senior Physical Design Engineer - USA-CA San Jose Innovation Drive, United States
$121,900 - $195,000 USD yearly
Originally posted 27 October 2026 by the employer.
Physical design execution from floorplanning to signoff in 5nm, 3nm, and 2nm nodes for Artificial Intelligence and PCIe switch products.
About the role
Broadcom is searching for a Senior Physical Design Engineer to join the ASIC Products Division. This position covers all physical design aspects of taking RTL to silicon tape-out for Artificial Intelligence and PCIe switch products.
What you'll do
- Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus. - Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks. - Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk.
What you'll need
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field. - 8+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs. - Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes. - High proficiency in Cadence Innovus for P&R, and Synopsys PrimeTime or Cadence Tempus for Timing/STA. - Experience with StarRC / QRC, RedHawk for extraction and IR/EM, and Siemens Calibre for DRC/LVS. - Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
Nice to have
- Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS). - Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
Skills: Innovus, STA, PrimeTime, floorplanning, CTS, P&R
This role has been open 0 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 682 |
| Open roles in the wider Physical Implementation family | 44 | 1530 · 112 employers |
| Median days open | 97 d | 66 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Innovus, STA, PrimeTime, floorplanning, CTS, P&R
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom (this employer) · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.