Senior Performance Modeling Architect, CPU Fabric and LLC
$152,000 - $241,500 USD yearly
Build cycle-accurate C++ and SystemC performance models for coherent fabrics and L3/System Cache hierarchies.
Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
NVIDIA is looking for a Senior Performance Modeling Architect to define and optimize CPU cache hierarchies and interconnects. You will build performance models for next-level caches (L3/System Cache) and coherent fabrics spanning automotive and data center architectures.
What you'll do
- Develop and maintain high-fidelity, cycle-accurate performance models in C++ and SystemC for coherent interconnects and large-scale shared caches.
- Model and analyze performance bottlenecks across architectures ranging from small-cluster automotive SoCs to multi-mesh data center systems.
- Evaluate the performance impact of coherency protocols, such as CHI, ACE, or proprietary implementations, and snooping filters.
- Run and analyze industry-standard benchmarks including SPEC, MLPerf, and automotive-specific suites to drive architectural trade-offs.
- Collaborate with build and verification teams to correlate performance models with silicon, and work with software teams to optimize drivers for hardware topology.
What you'll need
- Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience) with a focus on architecture and 5+ years of experience.
- Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
- Experience in C++ or SystemC for cycle-accurate or functional modeling.
- Proficiency in Python or similar scripting languages for processing datasets, generating performance visualizations, and automating simulation sweeps.
- Understanding of Network-on-Chip (NoC) topologies (Mesh, Ring, Torus), credit-based flow control, and arbitration logic.
Skills: performance modeling, cycle-accurate models, coherent interconnects, cache coherency protocols, Network-on-Chip (NoC)
More semiconductor jobs: NVIDIA jobs · SoC design jobs · California jobs
This role has been open 177 days — well above the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
469
|
Median days open
72 d
|
Category median salary (all employers)
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (469 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 469 |
| Open roles in the wider Digital Design & Verification family | 257 | 3354 · 114 employers |
| Median days open | 73 d | 72 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: performance modeling, cycle-accurate models, coherent interconnects, cache coherency protocols, Network-on-Chip (NoC)
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA (this employer) · 52 open roles · median 71 d
- Apple · 44 open roles · median 22 d
- AMD · 39 open roles · median 60 d
- Arm Holdings · 30 open roles · median 3 d
- Micron Technology · 21 open roles · median 107 d
How we counted: 469 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.