Senior PDK Reliability Engineer - United States
$173,660 - $245,160 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
This role involves driving design enablement in quality and reliability on Intel technology nodes, focusing on supporting customer design on Intel Si and package technologies.
What you'll do
- Define and generate reliability-related PDK design rules and collateral, including QA and benchmarking analysis.
- Drive industry EDA tool and flow enablement in synergy with PDK development.
- Perform competitive analysis and benchmarking of technology reliability.
What you'll need
- Bachelor's degree in electrical engineering, physics, or a related field with 6+ years of relevant experience, or Master's degree with 4+ years, or PhD with 2+ years.
- 3+ years' experience in one of the following: PDK development, reliability tool and flow, design for reliability, Circuit, IP, and SOC design reliability validation using PDK, EDA tool, and flow development.
Nice to have
- Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.
- Hands-on experience on PDK development and validation.
- Knowledge and understanding of PDK fundamentals.
- Knowledge of reliability design rules and their implementation in PDK and TFM.
- Capability to use AI or program skills to write code, agent, or script for design rule, techfile generation, and quality assurance.
- Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off.
- Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).
Skills: PDK development, design rule, EDA tool, design for reliability, TFM
This role has been open 0 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
682
|
Median days open
85 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (682 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 682 |
| Open roles in the wider Physical Implementation family | 45 | 1414 · 108 employers |
| Median days open | 27 d | 85 d (−58 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: PDK development, design rule, EDA tool, design for reliability, TFM
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 148 d
- Synopsys · 55 open roles · median 62 d
- NVIDIA · 46 open roles · median 67 d
- Micron Technology · 37 open roles · median 118 d
- Qualcomm · 37 open roles · median 64 d
- Intel Corporation (this employer) · 28 open roles · median 28 d
How we counted: 682 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.