Senior Packaging Integration Lead - San Jose, California, United States
Originally posted 22 September 2026 by the employer.
Astera Labs provides rack-scale AI infrastructure through purpose-built advanced connectivity products.
About the role
This role involves end-to-end ownership of the packaging solution for one or more of Astera Labs’ advanced connectivity products. It focuses on defining package architecture and test vehicles to de-risk technology, guiding execution engineers, and working with external partners.
What you'll do
- Own the packaging solution for assigned products from definition through development, qualification, and production ramp.
- Act as the primary packaging interface to customers, translating requirements into package architecture and execution roadmaps.
- Define package architecture, structure, and technology selection (e.g., 2.5D/3D integration, chiplet/interposer, CoWoS-class, organic substrate) with trade-off analysis.
- Define and drive test vehicle strategy to de-risk new package technology, characterize SIPI performance, and validate assembly and reliability.
- Represent packaging across internal cross-functional teams and align packaging requirements to product and business-unit roadmaps.
- Set technical direction with OSAT, foundry, and substrate partners, driving technology selection and development roadmaps.
What you'll need
- B.S. or M.S. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related discipline.
- 5-7+ years of experience in advanced packaging technologies such as 2.5D/3D integration, TSV, chiplets, and interposers.
- Demonstrated end-to-end ownership of a product or platform packaging solution, from definition and architecture through qualification and production ramp.
- Experience defining package architecture and driving technology selection, including trade-off analysis across performance, cost, reliability, and manufacturability.
Nice to have
- Optical / co-packaged optics experience.
Skills: advanced connectivity products, package architecture definition, 2.5D/3D integration, chiplet/interposer, CoWoS-class
This role has been open 0 days — well below the 40-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
66
|
Median days open
40 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (66 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 66 |
| Median days open | 180 d | 40 d (+140 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: advanced connectivity products, package architecture definition, 2.5D/3D integration, chiplet/interposer, CoWoS-class
Who's hiring in this category
- Micron Technology · 13 open roles · median 145 d
- AMD · 6 open roles · median 29 d
- Marvell Technology · 6 open roles · median 15 d
- Broadcom · 5 open roles · median 165 d
- NVIDIA · 5 open roles · median 40 d
- Amazon · 3 open roles · median 14 d
How we counted: 66 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.