Senior Mixed-Signal Verification Engineer -Power Management ICs - Remote
Focus on mixed-signal verification for high-current IVR designs.
About the role
This role involves developing and executing mixed-signal verification for power management ICs, focusing on high-current IVR designs.
What you'll do
- Develop and execute mixed-signal verification plans for high-current IVR designs.
- Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling).
- Perform analog-digital co-simulation using industry-standard tools (Cadence Xcelium + Spectre, Synopsys VCS + FineSim / CustomSim, or AMS Designer).
- Verify digital control loops.
- Create testbenches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
- Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
- Debug mixed-signal issues at both transistor-level and behavioral level.
- Collaborate with analog designers, digital designers, and system engineers to close verification coverage.
- Develop automated verification scripts and improve verification methodology.
- Support post-silicon validation by correlating simulation results with lab measurements.
What you'll need
- 5+ years of hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
- Proficiency in mixed-signal simulation flows, including Real Number Modeling (RNM) and Verilog-A behavioral modeling.
- Experience with analog-digital co-simulation (AMS, VCS + Spectre, Xcelium).
- Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
- Knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
- Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
- Proficiency in SystemVerilog and UVM for digital/mixed-signal testbenches.
- Familiarity with Cadence Virtuoso, Spectre, or Synopsys CustomSim for analog simulation.
- Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
- BSEE / MSEE with 8+ years relevant experience.
Skills: mixed-signal verification, power management ICs, analog behavioral models, analog-digital co-simulation, digital control loops, Verilog-A
This role has been open 20 days — well below the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 173 |
| Open roles in the wider Analog & Mixed-Signal family | 7 | 1317 · 100 employers |
| Median days open | 20 d | 79 d (−59 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: mixed-signal verification, power management ICs, analog behavioral models, analog-digital co-simulation, digital control loops, Verilog-A
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm · 10 open roles · median 55 d
- Microchip Technology · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.