Senior Mask Layout Design Engineer
Analog & Mixed-Signal Design
Originally posted 25 June 2026 by the employer — open 77 days.
This role involves physical layout for high speed memory I/O circuits, SerDes, and PLL's.
About the role
This role involves performing physical layout for high-speed mixed-signal circuit designs.
What you'll do
- Perform physical layout for PLL's, high speed memory I/O circuits, SerDes, general I/O's, and ESD structures designs.
- Customize designs for integration in VLSI products.
- Handle floor planning, custom layout, and verification against design rules and schematics.
- Run and debug DRC and LVS with verification tools.
What you'll need
- BSEE with a minimum of 5 years of relevant mask design / layout experience.
- Understanding of analog circuit layout concepts in submicron CMOS technologies.
- Expertise with Cadence custom circuit design tools, particularly Virtuoso.
- Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre.
- Proficiency in scripting languages like Perl, Python, Skill.
- Knowledge of DRC and LVS checking flows and ability to customize DRC and LVS decks.
Skills: mask layout, Cadence Virtuoso, DRC LVS, FinFET, PLL high-speed I/O
Market context
This role has been open 77 days — below the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in category | 12 | 173 |
| Median days open | 51 d | 79 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: mask layout, Cadence Virtuoso, DRC LVS, FinFET, PLL high-speed I/O
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA (this employer) · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm · 10 open roles · median 55 d
- Microchip Technology · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.