Senior Manager, ASIC Design Engineering

About the role

This role involves leading and growing the RTL design engineering team, driving full-lifecycle development of high-performance networking ASICs, and managing a team of talented design engineers.

What you'll do

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress.
• Utilize data-driven insights to predict schedule risks and reallocate human resources.
• Align RTL delivery schedules with DV and emulation enablement, managing feedback loops and dependencies.
• Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints.
• Lead long-term headcount planning and organizational design for the ASIC department.

What you'll need

• 15+ years in the semiconductor industry, with at least 5 years in people management.
• B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience.
• Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams.
• Proven ability to lead engineering organizations through multiple full-cycle ASIC product launches.
• Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).

Nice to have

• Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration.
• Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment.

More semiconductor jobs: RTL design jobs · Austin jobs