Senior Manager - Analog Design - MA, Boxborough, United States
Originally posted 22 May 2026 by the employer — open 111 days.
About the role
This role involves managing the Memory I/O design team, focusing on the definition, specification, system simulation, and implementation of future LPDDR IPs.
What you'll do
- Manage and contribute to the definition of circuit architecture and design implementation of low power, area efficient circuits for LPDDR PHYs.
- Collaborate with Analog Mixed Signal design, Digital Design, Firmware, and Design Verification to ensure optimal PHY architecture and algorithms.
- Manage execution and deliverables across customers and stakeholders.
- Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization).
- Document micro-architecture and algorithms, guiding Analog, Digital, Firmware, and Verification teams on circuit training and verification.
- Participate in defining development flows to improve efficiency and quality of execution.
What you'll need
- 5+ years of team management experience leading multiple IPs from design to production.
- Bachelor's, Master's or Ph.D. degree in Computer Engineering or Electrical Engineering.
- Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
- Solid knowledge of industry-standard tools and practices for PHY modeling, including abstracted models (e.g., Matlab/Simulink) and Verilog/AMS-based.
- Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Nice to have
- Proven track record of successfully leading execution of multiple PHY designs with good Silicon results.
- Proven successful track record in circuit-architecture and modeling for High Speed IOs.
- Ability to dig into RTL or FW code supporting custom circuit implementation.
Skills: LPDDR PHYs, high-speed IOs, circuit architecture, link performance simulations, equalization
This role has been open 110 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 24 | 217 |
| Median days open | 61 d | 91 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: LPDDR PHYs, high-speed IOs, circuit architecture, link performance simulations, equalization
Who's hiring in this category
- AMD (this employer) · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.