Analog & Mixed-Signal Design
$210,000 - $280,000 USD yearly
Architect and implement custom clock distribution networks and ESD/Latch-Up strategies in FinFET and GAA nodes.
Originally posted 5 November 2026 by the employer.
About the role
As a Senior / Lead VLSI Design Engineer, you will serve as the architect and hands-on owner for global circuit areas including custom clocking, low-power design techniques, and power distribution integrity, while leading chip-level PLL, IO, ESD, and Latch-Up strategy and integration.
What you'll do
- Architect, design, and perform transistor-level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks such as H-trees, grids, meshes, or hybrid topologies.
- Perform comprehensive signal integrity (SI), power integrity (PI), jitter, skew, and EM/IR analyses across chip-level clock distribution networks.
- Drive low-power design methodology, power analysis of key components, and power distribution integrity analysis.
- Collaborate with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis (CTS) guidelines.
- Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures specified by ESD/Latch-Up methodology.
- Drive pre-silicon chip-level reliability and clock timing sign-off before tape-out, supporting post-silicon bring-up.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics.
- 8+ years of custom analog/mixed-signal VLSI design experience in advanced process nodes such as FinFET / GAA (e.g., 7nm, 5nm, 3nm, 2nm).
- Experience designing custom clock networks, low-power design techniques, and custom IO/ESD/Latch-Up circuits.
- Deep knowledge of physical layout requirements for high-speed clocking, parasitic extraction, and low-resistance interconnects.
- Hands-on experience with transistor-level circuit simulators, transmission line theory, jitter and skew analysis methodology, PERC, ESD, EM/IR analysis, and parasitic extraction tools.
- Familiarity with semiconductor foundry ESD and Latch-Up design rules, guard-ring guidelines, and sign-off flows across advanced nodes.
Nice to have
- MS/Ph.D. in Electrical Engineering with experience on custom Analog/Mixed-Signal IC Design or silicon reliability.
- 10+ years of industry experience driving complex top-level silicon integrations.
- Experience utilizing scripting languages such as Python, TCL, or SKILL for flow automation and simulation post-processing.
Skills: clock distribution, PLL, ESD, Latch-Up, FinFET, transistor level
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