Senior Lead STA Engineer - Noida, Uttar Pradesh, India
Originally posted 22 September 2026 by the employer.
About the role
This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for high-performance, high-quality, low-power products. You will focus on static timing analysis aspects of ASIC development.
What you'll do
- Perform static timing analysis and constraints development.
- Solve critical timing bottleneck paths.
- Prepare complex ECOs for timing convergence across various corners.
- Minimize power consumption through implementation methods.
- Push PPA (Power, Performance, Area) to its best possible extent.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- 5 years of experience in static timing analysis, constraints, and other physical implementation aspects.
- Solid understanding of industry standard tools PT, Tempus, GENUS, Innovus, ICC.
- Experience about preparing complex ECOs for timing convergence through Tweaker / Tempus / Physical PT ECOs.
- Expertise in Perl, TCL language.
Nice to have
- Experience in deep submicron process technology nodes.
- Knowledge of high performance and low power implementation methods.
Skills: static timing analysis, STA, timing convergence, ECOs, PT, Tempus
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
633
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (633 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 633 |
| Open roles in the wider Physical Implementation family | 166 | 1414 · 108 employers |
| Median days open | 36 d | 61 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: static timing analysis, STA, timing convergence, ECOs, PT, Tempus
Who's hiring in this category
- Qualcomm (this employer) · 122 open roles · median 37 d
- Broadcom · 39 open roles · median 72 d
- NVIDIA · 38 open roles · median 47 d
- AMD · 36 open roles · median 38 d
- Synopsys · 27 open roles · median 61 d
- Renesas Electronics · 25 open roles · median 49 d
How we counted: 633 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.