Originally posted 22 September 2026 by the employer.
About the role
This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for high-performance, high-quality, low-power products. You will focus on static timing analysis aspects of ASIC development.
What you'll do
- Perform static timing analysis and constraints development.
- Solve critical timing bottleneck paths.
- Prepare complex ECOs for timing convergence across various corners.
- Minimize power consumption through implementation methods.
- Push PPA (Power, Performance, Area) to its best possible extent.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- 5 years of experience in static timing analysis, constraints, and other physical implementation aspects.
- Solid understanding of industry standard tools PT, Tempus, GENUS, Innovus, ICC.
- Experience about preparing complex ECOs for timing convergence through Tweaker / Tempus / Physical PT ECOs.
- Expertise in Perl, TCL language.
Nice to have
- Experience in deep submicron process technology nodes.
- Knowledge of high performance and low power implementation methods.
Skills: static timing analysis, STA, timing convergence, ECOs, PT, Tempus
More semiconductor jobs: Qualcomm jobs · Physical design jobs · India jobs
This role has been open 43 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
708
|
Median days open
63 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (708 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 708 |
| Open roles in the wider Physical Implementation family | 154 | 1591 · 117 employers |
| Median days open | 57 d | 63 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: static timing analysis, STA, timing convergence, ECOs, PT, Tempus
Who's hiring in this category
- Qualcomm (this employer) · 109 open roles · median 57 d
- AMD · 61 open roles · median 37 d
- Broadcom · 49 open roles · median 37 d
- NVIDIA · 45 open roles · median 78 d
- Synopsys · 43 open roles · median 36 d
- Intel Corporation · 33 open roles · median 27 d
How we counted: 708 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.