Senior Lead Physical Design Engineer - Noida, Uttar Pradesh, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves complete ownership of PNR implementation for Qualcomm SoCs.
What you'll do
- Own PNR implementation (Floorplanning, Placement, CTS, post_route) on latest nodes.
- Apply signoff knowledge (STA, Power analysis, FV, low power verification, PV).
- Perform Floorplanning, PNR, and STA flows.
- Implement Placement, Clock Tree Synthesis (CTS), and optimization.
- Apply knowledge of signoff domains including LEC/CLP/PDN.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- 5 years Hardware Engineering experience or related work experience.
- 5 years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
- Good knowledge of Unix/Linux – Perl/TCL fundamentals/scripting.
Skills: PNR implementation, Floorplanning, Clock Tree Synthesis, STA flows, signoff domains
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
601
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (601 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 112 | 601 |
| Open roles in the wider Physical Implementation family | 155 | 1388 · 105 employers |
| Median days open | 40 d | 57 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PNR implementation, Floorplanning, Clock Tree Synthesis, STA flows, signoff domains
Who's hiring in this category
- Qualcomm (this employer) · 103 open roles · median 42 d
- Broadcom · 38 open roles · median 67 d
- NVIDIA · 38 open roles · median 48 d
- AMD · 34 open roles · median 41 d
- Synopsys · 28 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 44 d
How we counted: 601 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.