Provide architectural ownership and technical leadership for chiplet-based packaging, UCIe, silicon interposers, and advanced RDL.
Originally posted 19 October 2026 by the employer.
About the role
Axiado is hiring a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-Package (SiP) architectures. The role spans 2D and RDL-based fan-out (2.5D), chiplet-based designs, and heterogeneous integration from technology pathfinding through production ramp.
What you'll do
- Own package architecture and technology roadmaps, defining chiplet-based strategies including UCIe, silicon interposers, and advanced RDL.
- Perform and guide package design and physical layout for high-speed interfaces, including PCIe, CXL, LPDDR5, and UCIe.
- Define substrate stack-ups, packaging materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
- Drive SI/PI, thermal, mechanical, and reliability trade-offs at both package and system levels.
- Direct technical engagements with OSATs, foundries, and substrate suppliers to ensure technology co-development and manufacturing readiness.
- Establish scalable design methodologies, reusable packaging flows, and best practices.
What you'll need
- BSEE or MSEE in Electrical Engineering or a related field.
- Minimum of 10+ years of IC packaging experience for SoCs, ASICs, or memory products.
- Hands-on expertise in Flip-Chip BGA (FCBGA), System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe).
- End-to-end technical leadership experience on packaging programs from early architecture through high-volume production.
- Experience with high-speed SerDes package development for interfaces such as PCIe Gen5, LPDDR5 / LPDDR5X, USB 3.x, or 10G.
- Proven track record defining die-to-die and chiplet-based RDL/bump architectures and working directly with OSATs, foundries, and substrate vendors.
Nice to have
- PhD in Electrical Engineering or related field.
- Proficiency with Cadence Allegro Package Designer (APD) or equivalent EDA tools.
- SI/PI expertise, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
- Experience building new packaging methodologies or platforms from scratch.
Skills: UCIe, chiplet, interposer, RDL, FCBGA, SI/PI
More semiconductor jobs: Advanced packaging jobs
First seen in our index 0 days ago, well below the 49-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
74
|
Median days since first seen
49 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Axiado | All employers we track in this specialty (74 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 74 |
| Median days since first seen | 0 d | 49 d (+49 d vs this employer) |
| Median salary (USD postings) | n/a | $176k |
Skills observed across this category: UCIe, chiplet, interposer, RDL, FCBGA, SI/PI
Who's hiring in this category
- AMD · 11 open roles · median 28 d
- Micron Technology · 9 open roles · median 195 d
- Marvell Technology · 7 open roles · median 43 d
- NVIDIA · 6 open roles · median 65 d
- Qualcomm · 5 open roles · median 85 d
- Intel Corporation · 4 open roles · median 49 d
How we counted: 74 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 26 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.