$184,000 - $356,500 USD yearly
Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
As a Senior GPU System Architect at NVIDIA, you will architect and design multi-GPU scale-up and scale-out systems for datacenter platforms for AI and HPC. You will explore and define system architectures that couple GPU compute, high-bandwidth memory, in-package interconnects, and GPU-to-GPU communication fabric subsystems.
What you'll do
- Architect multi-GPU system topologies for scale-up and scale-out configurations, balancing AI throughput, scalability, and resilience.
- Define, modify, and evaluate architectures for high-speed interconnects including NVLink and Ethernet co-designed with the GPU memory system.
- Architect RDMA-capable hardware and define transport layer optimizations for GPU-based large scale AI workload deployments.
- Use and modify system models, perform simulations, and run bottleneck analyses to guide design trade-offs.
- Work with GPU ASIC, compiler, library, and software stack teams to enable hardware-software co-design across compute, memory, and communication layers.
- Contribute to interposer, package, PCB, and switch co-design for high-density multi-die, multi-package, multi-node rack-scale systems consisting of hundreds of GPUs.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
- 8 or more years of experience in system design or ASIC/SoC architecture for GPU, CPU, or networking products.
- Deep understanding of communication interconnect protocols including NVLink, Ethernet, InfiniBand, CXL, and PCIe.
- Experience with RDMA/RoCE or InfiniBand transport offload architectures.
- Demonstrated ability to architect multi-GPU/multi-CPU topologies with awareness of bandwidth scaling, NUMA, memory models, coherency, and resilience.
- Experience with hardware-software interaction, drivers and runtimes, and performance tuning for distributed computing systems.
- System modeling skills using Python, SystemC, or similar tools.
Skills: multi-GPU system topologies, NVLink, Ethernet, chiplet interconnect architectures, 2.5D/3D package co-design
More semiconductor jobs: NVIDIA jobs · SoC design jobs · California jobs
This role has been open 176 days — well above the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
469
|
Median days open
72 d
|
Category median salary (all employers)
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (469 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 469 |
| Open roles in the wider Digital Design & Verification family | 257 | 3355 · 114 employers |
| Median days open | 73 d | 72 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: multi-GPU system topologies, NVLink, Ethernet, chiplet interconnect architectures, 2.5D/3D package co-design
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA (this employer) · 52 open roles · median 71 d
- Apple · 44 open roles · median 22 d
- AMD · 39 open roles · median 60 d
- Arm Holdings · 30 open roles · median 3 d
- Micron Technology · 21 open roles · median 107 d
How we counted: 469 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.