Originally posted 6 August 2026 by the employer.
About the role
This role involves executing full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components. You will provide technical leadership and mentor junior layout engineers.
What you'll do
- Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components.
- Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends.
- Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks.
- Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity.
- Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration (EM) guidelines.
- Provide technical leadership during project execution and mentor junior layout engineers.
What you'll need
- Bachelor's or master's degree in electrical engineering or a comparable field.
- 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies.
- High proficiency with industry-standard EDA tools (Cadence Virtuoso, Siemens Calibre).
- Excellent analytical skills to independently debug complex layout and physical verification issues.
- Ability to guide, motivate, and coordinate small layout teams during project execution.
- Ability to collaborate closely with ADC Design Engineers.
Skills: full-custom IC layout, ADC mixed-signal, physical verification, DRC, LVS, Cadence Virtuoso
This role has been open 53 days — well below the 94-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
155
|
Median days open
94 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (155 roles · 42 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 155 |
| Open roles in the wider Analog & Mixed-Signal family | 66 | 1377 · 105 employers |
| Median days open | 78 d | 94 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: full-custom IC layout, ADC mixed-signal, physical verification, DRC, LVS, Cadence Virtuoso
Who's hiring in this category
- Analog Devices · 24 open roles · median 79 d
- Infineon Technologies (this employer) · 14 open roles · median 82 d
- SiTime · 11 open roles · median 191 d
- NVIDIA · 10 open roles · median 49 d
- Qualcomm · 8 open roles · median 59 d
- Broadcom · 7 open roles · median 37 d
How we counted: 155 open Mixed-Signal Design (Mixed Signal) roles from 42 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.