Senior Engineer II - Physical Design - Canada - Burnaby, Canada
$86,000 - $186,000 USD yearly
Originally posted 17 September 2026 by the employer — open 2 days.
About the role
This role involves executing chip development methodologies as a key member of the Implementation team.
What you'll do
- Execute block level place and route and physical design verification.
- Develop macro level test structures and digital wrappers for analog cells.
- Perform synthesis and static timing for high-performance devices.
- Support customers through Microchip's Chip development flow.
- Collaborate with CAD, Packaging, Mixed Signal, Operations, and Design teams.
- Implement chip level, subsystem, CPU, and mixed signal blocks.
What you'll need
- 4-year degree in Electrical or Electronics Engineering with 7.5+ years of ASIC development experience.
- Design, Synthesis, Static Timing and Place & Route experience in high performance design.
- Hands-on experience in floorplanning, placement optimization, clock tree synthesis, and physical verification.
- Recent experience with full chip Physical Design activities.
- Understanding of Verilog and VHDL languages.
- Proficiency in Python/PERL/TCL scripting.
Nice to have
- Experience with 6nm process or lower.
Skills: block level place and route, physical design verification, floorplanning, placement optimization, clock tree synthesis
This role has been open 2 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
603
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (603 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 603 |
| Open roles in the wider Physical Implementation family | 26 | 1371 · 106 employers |
| Median days open | 87 d | 58 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: block level place and route, physical design verification, floorplanning, placement optimization, clock tree synthesis
Who's hiring in this category
- Qualcomm · 108 open roles · median 41 d
- Broadcom · 38 open roles · median 68 d
- NVIDIA · 38 open roles · median 49 d
- AMD · 35 open roles · median 38 d
- Synopsys · 27 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 45 d
How we counted: 603 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.