Senior Engineer II - Layout
$70,304 - $205,000 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
As a Senior Engineer II - Layout on the Layout Engineering team, you will support complex semiconductor physical layout, integration, extraction, verification, manufacturability, reliability, and design-closure challenges.
What you'll do
- Define and execute layout architectures, floorplans, device structures, interconnect, power distribution, matching, shielding, extraction, and verification strategies.
- Integrate circuit, interface, technology, performance, power, area, reliability, manufacturability, design-rule, and schedule requirements.
- Resolve layout, connectivity, parasitic, matching, coupling, electromigration, physical-verification, integration, and tapeout-readiness issues.
- Establish reusable layout structures, automation, verification, extraction, design-rule, and release practices.
- Review requirements, floorplans, layouts, extracted results, reports, waivers, defects, and release evidence.
What you'll need
- Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field.
- 7.5–10 years of relevant experience in semiconductor layout, custom physical design, analog, digital, mixed-signal, memory, IO, ASIC or SoC layout.
- Experience with floorplanning, device placement, routing, extraction, physical verification, or closely related equivalent domains.
- Demonstrated ability to work with complex design rules, schematics, devices, interconnect, parasitics, reliability, manufacturing, and signoff information.
Nice to have
- Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field.
- Experience with semiconductor custom, analog, digital, mixed-signal, memory, IO, pad, RF, ASIC, or SoC layout.
- Experience with floorplanning, device placement, routing, matching, shielding, power distribution, extraction, DRC, LVS, ERC, antenna, density, reliability, or physical-verification closure.
- Experience with layout and physical-verification tools, scripting, automation, process-design kits, advanced process nodes, or design-for-manufacturing methods.
Skills: DRC, LVS, physical verification, custom layout, parasitic extraction, floorplanning
More semiconductor jobs: Microchip Technology jobs · Analog design jobs
This role has been open 0 days — well below the 26-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
86
|
Median days open
26 d
|
Category median salary (all employers)
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (86 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 86 |
| Open roles in the wider Analog & Mixed-Signal family | 34 | 1533 · 113 employers |
| Median days open | 0 d | 26 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: DRC, LVS, physical verification, custom layout, parasitic extraction, floorplanning
Who's hiring in this category
- Analog Devices · 9 open roles · median 45 d
- Renesas Electronics · 8 open roles · median 28 d
- Micron Technology · 7 open roles · median 9 d
- onsemi · 7 open roles · median 32 d
- Infineon Technologies · 6 open roles · median 20 d
- Marvell Technology · 6 open roles · median 40 d
How we counted: 86 open Analog IC Design (Analog Layout) roles from 29 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.