Senior Engineer II - CAD (Physical Verification)
Originally posted 9 September 2026 by the employer.
About the role
This role focuses on developing and supporting physical verification flows for semiconductor chip design within the CAD group, providing innovative solutions for the design community.
What you'll do
- Develop physical verification regression test cases to QA physical verification decks.
- Support Layout and Design engineers with physical verification activities using tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules.
- Utilize knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, and via doubling methodologies.
- Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks.
- Develop and verify rule decks to support flow and enhance foundry rule decks.
- Support remote sites worldwide with layout verification activities and debug physical verification issues.
What you'll need
- Bachelors in Electrical Engineering or related field with 7.5 to 10 years experience developing and supporting physical verification activities.
- In depth knowledge of Calibre DesignRev scripting.
- Fluent with SVRF and TVF.
- Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer.
- Familiar with customizing Calibre Interactive.
- Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools.
- Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules.
- Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs.
- Strong knowledge of Cadence Virtuoso and/or CalibreDRV.
Nice to have
- Masters in Electrical Engineering or related field.
- Extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool.
- Extraction, Reliability and Dynamic Noise related knowledge.
- Experience supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
- Experience with Calibre/Pegasus PERC setup for several PDKs.
Skills: Calibre, Pegasus, DRC, LVS, PERC, SVRF, TVF
More semiconductor jobs: Microchip Technology jobs · EDA tools engineer jobs · India jobs
This role has been open 56 days — well below the 66-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
723
|
Median days open
66 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (723 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 723 |
| Open roles in the wider Physical Implementation family | 29 | 1591 · 117 employers |
| Median days open | 47 d | 66 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Calibre, Pegasus, DRC, LVS, PERC, SVRF
Who's hiring in this category
- Cadence Design Systems · 158 open roles · median 161 d
- Synopsys · 59 open roles · median 54 d
- Micron Technology · 48 open roles · median 42 d
- NVIDIA · 41 open roles · median 100 d
- Renesas Electronics · 38 open roles · median 13 d
- Qualcomm · 34 open roles · median 86 d
How we counted: 723 open EDA/CAD Engineering (EDA Tools) roles from 78 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.