Senior Engineer Analog Layout - Penang, Malaysia
Originally posted 12 August 2026 by the employer.
About the role
This role involves performing analog circuit block, subsystem, and top-level layout and verification for advanced IC designs. The position focuses on layout design of Analog circuits (block/IP/chip) floor planning from scratch, including routing and layout verification.
What you'll do
- Perform analog circuit block, subsystem and top-level layout and verification using state-of-the art tools (Cadence Virtuoso--VXL).
- Participate in layout design of Analog circuits (block/IP/chip) floor planning from scratch.
- Perform routing & layout verification and resolve violations.
- Participate in layout design reviews.
- Plan block level schedule.
What you'll need
- Bachelor's Degree in Electrical, Electronics Engineering, or Microelectronics with VLSI exposure.
- 2 - 5 years of job experience in Analog Layout.
- Hands-on experience in analog layout from scratch and implementation of analog layout techniques.
- Understanding and hands-on experience in IR drop/EM analysis.
- Good understanding of Analog circuit layout concepts in submicron CMOS technologies.
- Understanding on matching, parasitic reduction, ESD, DFM.
Skills: analog circuit block layout, Cadence Virtuoso, floor planning, routing & layout verification, CMOS technologies
This role has been open 48 days — well above the 25-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
49
|
Median days open
25 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 49 |
| Open roles in the wider Analog & Mixed-Signal family | 67 | 1385 · 107 employers |
| Median days open | 41 d | 25 d (+16 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: analog circuit block layout, Cadence Virtuoso, floor planning, routing & layout verification, CMOS technologies
Who's hiring in this category
- Celero · 8 open roles · median 32 d
- Analog Devices · 7 open roles · median 12 d
- Marvell Technology · 4 open roles · median 16 d
- Broadcom · 3 open roles · median 8 d
- onsemi · 3 open roles · median 35 d
- QORVO · 3 open roles · median 33 d
How we counted: 49 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.