Senior Director, Central Engineering – SoC Design & Modeling Methodologies - San Jose, United States
Originally posted 28 October 2026 by the employer.
About the role
This position serves as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture across Central Engineering.
What you'll do
- Define and drive the strategic roadmap for workload analysis and performance for IPs and products across the organization. - Lead architecture performance reviews and set technical direction for complex IP/SoC and subsystem developments. - Establish best practices for hardware/software co-design and model-based development. - Define and analyze AI workloads and evaluate the performance required for these workloads. - Provide technical leadership to cross-functional teams spanning architecture, design, verification, emulation, and software. - Build and mentor engineering teams, including directors, principal engineers, and distinguished engineers.
What you'll need
- MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - 15+ years of experience in semiconductor or SoC development. - 8+ years of technical leadership experience. - Hands-on experience with performance and workload benchmarking, SoC performance modeling, virtual platforms, and executable specifications. - Deep expertise leading performance and workload analysis, HW/SW co-optimization, and SoC architecture and integration. - Direct experience with design and verification automation flows, digital design methodologies, and IP and subsystem development.
This role has been open 0 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
487
|
Median days open
76 d
|
Median salary
$237k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (487 roles · 69 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 487 |
| Open roles in the wider Digital Design & Verification family | 81 | 3361 · 116 employers |
| Median days open | 82 d | 76 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $237k |
Who's hiring in this category
- Qualcomm · 77 open roles · median 92 d
- NVIDIA · 53 open roles · median 71 d
- Apple · 44 open roles · median 20 d
- AMD · 40 open roles · median 61 d
- Arm Holdings · 31 open roles · median 79 d
- Micron Technology · 21 open roles · median 105 d
How we counted: 487 open SoC/Chip Architecture (SOC Architecture) roles from 69 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.