Senior Digital PD Engineer - Bengaluru, Karnataka, India
Originally posted 22 September 2026 by the employer.
About the role
This role involves working on high-speed mixed-signal communication circuits and high-performance digital circuits that interface with analog circuitry as part of an overall system.
What you'll do
- Act as the global quality authority for the digital backend, owning sign-off for the complete RTL to GDSII flow.
- Orchestrate collaboration with EDA, Library, Memory, and IP teams to align execution priorities and improve implementation.
- Define and establish TI-wide physical design methodologies and flows, optimized for the latest process nodes.
- Drive the entire Physical Design lifecycle, including floorplanning, placement, CTS, routing, and full-chip implementation.
- Lead rigorous Static Timing Analysis (STA) and ensure total closure for EM, IR drop, and Physical Verification (DRC/LVS).
What you'll need
- 12+ years of hands-on experience in Physical Design / Digital Backend implementation.
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or VLSI Design.
- Proven expertise in RTL-to-GDSII flows using industry-standard EDA tools (Synopsys and/or Cadence toolchain).
- Demonstrated ability to own and deliver complex designs independently from specification through signoff.
- Deep knowledge of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC).
- Strong understanding of process node design rules and implementation constraints.
Nice to have
- 12–18 years of progressive experience in physical design with increasing ownership and scope.
- Hands-on experience with mixed-signal designs — including analog-digital co-design, guard-ring strategies, substrate coupling mitigation, and mixed-signal floor planning.
- Prior experience in a Subject Matter Expert, methodology lead, or technical architect capacity.
- Familiarity with in-house or customized EDA flow development and scripting (Tcl, Python, Perl).
- Knowledge of DFT integration within the physical design flow (scan insertion, BIST, boundary scan).
- Exposure to power management architectures and low-power implementation techniques (multi-Vt, power gating, voltage islands).
Skills: RTL-to-GDSII, floorplanning, placement, CTS, routing, timing closure
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
633
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (633 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 633 |
| Open roles in the wider Physical Implementation family | 17 | 1414 · 108 employers |
| Median days open | 15 d | 61 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL-to-GDSII, floorplanning, placement, CTS, routing, timing closure
Who's hiring in this category
- Qualcomm · 122 open roles · median 37 d
- Broadcom · 39 open roles · median 72 d
- NVIDIA · 38 open roles · median 47 d
- AMD · 36 open roles · median 38 d
- Synopsys · 27 open roles · median 61 d
- Renesas Electronics · 25 open roles · median 49 d
How we counted: 633 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.