Senior Digital/AMS Validation and Integration Engineer - San Jose (Holger Way), United States
$166,200 - $228,500 USD yearly
Originally posted 13 March 2026 by the employer — open 181 days.
About the role
This role involves driving the integration of complex digital logic into Automotive SerDes transceivers, focusing on the RTL design of the Digital-Analog Wrapper. You will own the path from RTL through timing closure and support validation in the lab, specifically for 10G transceivers.
What you'll do
- Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths.
- Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing.
- Lead the digital implementation flow, working with physical design for timing closure in high-speed clock domains.
- Partner with the validation team to bring up silicon and exercise RTL features using Python-based tools.
- Debug state machines and verify registers (CSRs) in real-time hardware.
- Execute block-level and chip-level simulations to ensure digital control logic handles analog PVT variations and startup sequences.
What you'll need
- BSEE/MSEE with 5–8 years of experience in Digital RTL Design or Digital Integration.
- Advanced proficiency in SystemVerilog/Verilog for synthesis.
- Strong understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and constraints (SDC).
- Deep experience with Python or Perl for hardware control, test automation, and data processing.
- Proficient in using logic analyzers, high-speed scopes, and JTAG/I2C/SPI protocols for on-chip debugging.
Nice to have
- Experience with 10GBase-T, ASA, or Automotive Ethernet standards.
- Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE).
- Knowledge of DFT (Design for Test) and BIST (Built-In Self-Test) insertion for high-speed links.
- Able to create Verilog-A models.
Skills: RTL design of the Digital-Analog Wrapper, control loops, calibration engines, high-speed data paths in 10G transceivers, digital interface for analog blocks (ADCs, PLLs), Silicon Validation
This role has been open 176 days — well above the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in category | 2 | 173 |
| Median days open | 102 d | 79 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: RTL design of the Digital-Analog Wrapper, control loops, calibration engines, high-speed data paths in 10G transceivers, digital interface for analog blocks (ADCs, PLLs), Silicon Validation
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm · 10 open roles · median 55 d
- Microchip Technology · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.