Senior DFT Methodology Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 13 July 2026 by the employer.
About the role
NVIDIA is seeking a Senior DFT Methodology Engineer to implement test access mechanisms, memory BIST, scan, and DFX security methodology across complex semiconductor chips. The role spans architecture, RTL design, verification, pattern generation, and post-silicon validation partnering with cross-functional engineering teams.
What you'll do
- Implement designs in test access mechanisms, IEEE 1149.1, IEEE 1500, IEEE 1687, IEEE 1838, memory BIST, scan, memory dump, and DFX security methodology. - Architect, develop, and deploy DFT methodologies including RTL design, verification, and pattern generation. - Partner across cross-functional teams including timing, physical design, software, bringup, and production. - Mentor junior engineers on test designs and trade-offs involving cost and quality.
What you'll need
- Master’s degree (or equivalent experience) in Electrical Engineering or a related field with proven experience in DFT or related domains. - 10+ years of hands-on experience in SoC architecture, RTL design, and verification. - Experience in verification and validation of test patterns and logic on complex multi-million gate designs using vendor tools. - Exposure to cross-functional areas including RTL and clocks design, STA, place-and-route, and power. - Experience in silicon debug and bring-up on the ATE with understanding of pattern formats, failure processing, and test program development.
Nice to have
- Knowledge of DFT security and hardware system security.
Skills: DFT methodologies, test access mechanisms, I1149.1, I1500, memory BIST, scan, ATPG, silicon debug
This role has been open 98 days — well above the 60-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
246
|
Median days open
60 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (246 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 246 |
| Open roles in the wider Digital Design & Verification family | 229 | 3244 · 116 employers |
| Median days open | 30 d | 60 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT methodologies, test access mechanisms, I1149.1, I1500, memory BIST, scan
Who's hiring in this category
- AMD · 40 open roles · median 40 d
- NVIDIA (this employer) · 24 open roles · median 29 d
- Qualcomm · 23 open roles · median 103 d
- NXP Semiconductors · 19 open roles · median 43 d
- Synopsys · 14 open roles · median 27 d
- Micron Technology · 10 open roles · median 67 d
How we counted: 246 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.