Senior DfT Engineer - Chandler (Office), United States
Originally posted 9 July 2026 by the employer.
About the role
As a Senior DfT Engineer at NXP Semiconductors, you will be responsible for defining and implementing testability requirements across complex digital logic, analog and mixed-signal IPs, and standard macros.
What you'll do
- Collaborate with Product Definers, Design Leads, Test Leads, Product Engineers, Quality Engineers, and Validation Engineers to define chip testability requirements across Functional, Debug, and ATPG modes. - Implement DfT architectures for complex analog and mixed-signal IPs, standard macros (RAM, ROM, NVM, ADC, DAC), and digital logic. - Deliver RTL design using Verilog and System-Verilog. - Define verification plans, write tests, and debug features to achieve passing status in the chiptop level DV environment. - Perform scan insertion, optimization, length balancing, P&R-aware chain rerouting, test-point insertion, ATPG pattern generation, simulation, and debug. - Support test engineers during pattern debug on new silicon and customer returns, while maintaining comprehensive DfT architecture and design documentation.
What you'll need
- Master's degree in Electrical Engineering (MSEE) with coursework focused on digital design, RTL coding, DfT, computer architecture, or digital verification. - Minimum 3 years of experience in DfT, digital design, and architecture (seeking 3-8 years total experience). - Hands-on experience with RTL design using Verilog and System-Verilog. - Proven experience with scan insertion, test-point insertion, ATPG pattern generation, simulation, and debug. - Experience with verification plan definition and test execution in a chiptop level DV environment. - Ability to be on-site at least 3 days per week at the NXP Chandler office.
Skills: Testability of the chip, DfT, Scan insertion, ATPG patterns generation, Test-Point insertion, Chiptop level DV environment
This role has been open 103 days — well above the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
61 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 248 |
| Open roles in the wider Digital Design & Verification family | 129 | 3244 · 116 employers |
| Median days open | 43 d | 61 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: Testability of the chip, DfT, Scan insertion, ATPG patterns generation, Test-Point insertion, Chiptop level DV environment
Who's hiring in this category
- AMD · 41 open roles · median 42 d
- NVIDIA · 24 open roles · median 30 d
- Qualcomm · 23 open roles · median 104 d
- NXP Semiconductors (this employer) · 19 open roles · median 44 d
- Synopsys · 14 open roles · median 28 d
- Intel Corporation · 10 open roles · median 61 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.