Senior Design Verification Engineer - San Jose, California, United States
$148,500 - $165,000 USD yearly
Originally posted 27 October 2026 by the employer.
Verify high-speed PCIe Gen 6/Gen 7 and UALink connectivity silicon for rack-scale AI infrastructure.
About the role
As a Senior Design Verification Engineer, you will define and deliver verification for connectivity silicon supporting rack-scale AI infrastructure. You will own verification challenges within CCE2, delivering PCIe and UALink connectivity products.
What you'll do
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements. - Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality. - Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models. - Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCI behavior. - Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones. - Debug simulation failures using waveform analysis, logs, and assertions, and partner on silicon bring-up readiness.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. - Experience with UVM and SystemVerilog testbench architecture, development, and debug. - Verification background covering high-speed serial protocols such as PCIe.
Skills: UVM, SystemVerilog, PCIe, coverage closure, testbench
This role has been open 0 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1268 |
| Open roles in the wider Digital Design & Verification family | 60 | 3359 · 116 employers |
| Median days open | 73 d | 67 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, PCIe, coverage closure, testbench
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.