Originally posted 5 November 2026 by the employer.
About the role
As a Senior Design & Physical Implementation Engineer, you will develop process monitors and silicon characterization circuits used to evaluate device behavior, process variation, layout-dependent effects, and technology performance. This position spans circuit architecture and SPICE simulation through physical implementation, custom layout, silicon validation, and data analysis.
What you'll do
- Design process monitors, sensing and measurement blocks, and characterization circuits to evaluate device behavior, process variation, reliability, and layout-dependent effects.
- Perform transistor-level simulation and analog verification using SPICE-based design flows, including corner analysis, Monte Carlo simulation, and post-layout verification.
- Design and integrate supporting digital control and interface circuitry required for monitor operation and data collection.
- Develop custom layouts for analog and characterization circuit blocks, optimizing floorplans, placement, and routing for silicon correlation.
- Develop and maintain EDA automation and scripting tools, and analyze characterization data using Python.
- Correlate measured silicon results to simulation and support silicon bring-up, debug, validation, and root-cause investigations.
What you'll need
- BS with 8+ years, or MS/PhD with 5+ years of relevant industry experience in Electrical Engineering or a related field.
- Strong background in analog or mixed-signal IC design and transistor-level simulation.
- Deep understanding of CMOS device operation, process variation, mismatch, parasitics, and layout-dependent effects.
- Hands-on experience with physical design, physical implementation, custom layout, and post-layout verification methodologies.
- Experience with EDA scripting, automation, or workflow development.
- Proficiency with Python for engineering analysis and data processing.
Nice to have
- Experience with process monitors, silicon characterization structures, or technology development test vehicles.
- Experience evaluating device, circuit, or standard-cell behavior across process, voltage, temperature, and layout conditions.
- Experience correlating silicon measurements to simulation results and device models.
- Experience developing engineering automation, dashboards, or data-analysis workflows.
- Experience with advanced process technologies and variability characterization.
Skills: SPICE, custom layout, process monitors, analog verification, characterization circuits
More semiconductor jobs: Tokyo Electron jobs · Mixed-signal design jobs
This role has been open 0 days — well below the 113-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
161
|
Median days open
113 d
|
Category median salary (all employers)
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tokyo Electron | All employers we track in this specialty (161 roles · 40 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 161 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1530 · 112 employers |
| Median days open | 0 d | 113 d (−113 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: SPICE, custom layout, process monitors, analog verification, characterization circuits
Who's hiring in this category
- NVIDIA · 20 open roles · median 183 d
- Analog Devices · 15 open roles · median 97 d
- SiTime · 11 open roles · median 225 d
- Apple · 10 open roles · median 21 d
- Infineon Technologies · 9 open roles · median 112 d
- Microchip Technology · 8 open roles · median 224 d
How we counted: 161 open Mixed-Signal Design (Mixed Signal) roles from 40 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.