Senior Design Engineer, Coherent High Speed Interconnect - CA, Santa Clara, United States
Originally posted 22 July 2026 by the employer — open 50 days.
This role focuses on the architecture and design of high-speed coherent interconnects (NVLINK-C2C).
About the role
This role involves the architecture and design of high-speed coherent interconnects for mobile SoCs and GPUs. You will work on NVLINK-C2C, which enables integrated products with NVIDIA partners via chiplets.
What you'll do
- Architect and design high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs.
- Collaborate with architects, external partners, software engineers, and circuit designers.
- Enable integrated products with NVIDIA partners through chiplets.
What you'll need
- BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree.
- 8+ years of relevant design experience.
- Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, CHI.
- Understanding or experience with Link layer stacks including Data link layer and Physical layer.
- Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc.), PCIE, SerDes.
- Experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
- Strong working knowledge of Verilog or System Verilog.
Nice to have
- Advanced degrees (MS, PhD).
- History of mentoring junior engineers and interns.
Skills: coherent interconnects, NVLINK-C2C, chiplets, high speed interconnects, integrated products
This role has been open 152 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 217 |
| Median days open | 95 d | 91 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: coherent interconnects, NVLINK-C2C, chiplets, high speed interconnects, integrated products
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA (this employer) · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.