Senior CPU Power Architect - CA, Santa Clara, United States
$152,000 - $287,500 USD yearly
Originally posted 28 October 2026 by the employer.
Work on CPU power modeling and silicon correlation across Grace and Vera CPU Superchips.
About the role
This role drives and optimizes CPU power efficiency across the entire design cycle, from early architectural modeling through RTL implementation to silicon validation. Technical scope includes pre-silicon power estimation, silicon correlation, and optimization across Grace and Vera CPU Superchips.
What you'll do
- Model and estimate CPU power at C-model, RTL, and netlist stages using industry-standard tools. - Identify inefficiencies and drive design improvements in collaboration with architects, RTL designers, and physical design engineers. - Create targeted power characterization tests, including peak power and di/dt stress patterns, for both simulation and silicon. - Set up power measurement equipment and measure CPU power and performance in the lab, correlating silicon results with pre-silicon estimates to refine models. - Partner across multiple engineering disciplines to achieve target power efficiency without compromising performance.
What you'll need
- BS or MS in EE, CE, CS, or equivalent experience. - 5+ years of experience working in ASIC power measurement and optimization. - Strong understanding of leakage and dynamic power in VLSI circuits. - Experience with RTL and netlist power analysis tools such as PowerArtist, PrimeTime PX, or equivalent. - Familiarity with CPU microarchitecture and its impact on power, including CPU pipeline design, out-of-order execution, cache hierarchy, and branch prediction.
Skills: CPU microarchitecture, Power modeling, PowerArtist, PrimeTime PX, DVFS
This role has been open 0 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
487
|
Median days open
76 d
|
Median salary
$237k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (487 roles · 69 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 487 |
| Open roles in the wider Digital Design & Verification family | 227 | 3352 · 116 employers |
| Median days open | 71 d | 76 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $237k |
Skills observed across this category: CPU microarchitecture, Power modeling, PowerArtist, PrimeTime PX, DVFS
Who's hiring in this category
- Qualcomm · 77 open roles · median 92 d
- NVIDIA (this employer) · 53 open roles · median 71 d
- Apple · 44 open roles · median 20 d
- AMD · 40 open roles · median 61 d
- Arm Holdings · 31 open roles · median 79 d
- Micron Technology · 21 open roles · median 105 d
How we counted: 487 open SoC/Chip Architecture (SOC Architecture) roles from 69 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.