Senior Cell Modeling and Verification Engineer - CA, Santa Clara, United States

Originally posted 24 July 2026 by the employer.

About the role

As a Senior Cell Modeling and Verification Engineer on the NVIDIA VLSI team, you will develop behavioral models and verification for custom mixed-signal design cells used across ASIC products.

What you'll do

- Develop behavioral models and verification environments for custom mixed-signal design cells used across NVIDIA products. - Use Verilog, SystemVerilog, Perl, or Python, applying knowledge of PLL and high-speed interconnects to model, verify, and emulate mixed-signal designs. - Collaborate with cross-functional teams on library build, cell integration, ASIC verification, and DFT simulation. - Document, implement, and deliver verified RTL to achieve design targets.

What you'll need

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience). - 3+ years of relevant experience. - Hands-on experience with RTL simulation and waveform debug. - Strong understanding of Verilog HDL. - Scripting experience using Python or Perl. - Knowledge of fundamental digital design and logic design concepts.

Nice to have

- Previous digital design experience. - Previous experience running simulations in Verilog.

Skills: behavioral model, verification, mixed signal design cells, Verilog, SystemVerilog, simulations