Senior Cell Modeling and Verification Engineer - CA, Santa Clara, United States

Originally posted 24 July 2026 by the employer — open 48 days.

About the role

This role involves developing behavioral models and verification for custom mixed signal design cells. You will work on crafting power-efficient and performance-leading SoCs and GPUs.

What you'll do

• Develop behavioral models and verification for custom mixed signal design cells.
• Model, verify, emulate/prototype mixed-signal designs using Verilog, SystemVerilog, Perl, or Python.
• Collaborate with cross-functional teams on library build, cell integration, ASIC verification, and DFT simulation.
• Document, implement, and deliver fully verified and high performance RTL.

What you'll need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of relevant experience.
• Hands-on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.
• Scripting experience and skills using Python or Perl.
• Knowledge of fundamental digital design and logic design concepts.

Nice to have

• Previous digital design experience.
• Previous experience running simulations in Verilog.

Skills: behavioral model, verification, mixed signal design cells, Verilog, SystemVerilog, simulations