Senior Cache Coherency Architect
$152,000 - $287,500 USD yearly
Architect coherent interconnect systems for Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin platforms.
Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
As a Senior Cache Coherency Architect at NVIDIA, you will contribute to the architecture of cache-coherent interconnect and cache subsystems, covering architecture definition, modeling, and implementation. Work spans platforms including Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin across consumer graphics, automotive, and AI product lines.
What you'll do
- Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
- Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
- Collaborate with architects to align interconnect architecture with project power, performance, and area (PPA) requirements.
- Develop and maintain functional and performance models for the NoC fabric and IP units to support analysis and validation.
- Work with cross-functional design and verification teams across simulation, emulation, and formal methods to ensure implementations match specifications.
- Support silicon bring-up and post-silicon debug as needed.
What you'll need
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 5+ years of experience in processor design or other high-performance semiconductor designs.
- Understanding of cache coherency with hands-on experience in industry-standard protocols such as AXI, ACE, and CHI.
- Experience authoring specifications and designing cache-coherent interconnects.
- Strong understanding of system and memory subsystem architecture, focusing on cache-coherent interconnect.
- Experience developing coherent IP models (such as VIPs and BFMs) for simulation and emulation.
- Proficiency in C, C++, Python, and Verilog.
Skills: cache coherency, interconnect architecture, AXI, ACE, CHI, NoC fabric
More semiconductor jobs: NVIDIA jobs · SoC design jobs · California jobs
This role has been open 193 days — well above the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
469
|
Median days open
72 d
|
Category median salary (all employers)
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (469 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 469 |
| Open roles in the wider Digital Design & Verification family | 257 | 3355 · 114 employers |
| Median days open | 73 d | 72 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: cache coherency, interconnect architecture, AXI, ACE, CHI, NoC fabric
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA (this employer) · 52 open roles · median 71 d
- Apple · 44 open roles · median 22 d
- AMD · 39 open roles · median 60 d
- Arm Holdings · 30 open roles · median 3 d
- Micron Technology · 21 open roles · median 107 d
How we counted: 469 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.