Senior Analog Layout Engineer (Teradyne, Costa Rica) - Sunnyvale, CA, United States
Originally posted 10 August 2026 by the employer — open 31 days.
About the role
This role involves leading the physical layout and verification of complex analog and mixed-signal ASICs.
What you'll do
- Lead the layout design and integration of complex analog and mixed-signal ASIC blocks using Cadence Virtuoso. - Develop floorplans, placement, routing, and top-level integration strategies for advanced-node technologies, including FinFET. - Apply advanced layout techniques to ensure device matching, symmetry, shielding, substrate isolation, and noise control. - Perform and sign off on DRC, LVS, ERC, and parasitic extraction to support first-pass silicon success. - Support the layout of high-speed and precision analog circuits, including ADCs, DACs, PLLs, references, and SerDes-adjacent blocks. - Mentor junior layout engineers and contribute to team capability development.
What you'll need
- BS degree in Electronic Engineering, Electrical Engineering or related field. - 10+ years of hands-on experience in analog or mixed-signal IC layout. - Experience with advanced FinFET process technologies and deep-submicron analog design. - Experience with TSMC technology platforms. - Hands-on experience with Cadence Virtuoso. - Experience laying out complex analog blocks such as ADCs, DACs, PLLs, bandgaps, bias circuits, and analog interfaces. - Experience with high-speed and precision analog layout best practices. - Knowledge of semiconductor manufacturing processes and advanced design rules. - Ability to independently drive complex layout activities from concept through tape-out.
Skills: analog layout, mixed-signal ASIC, Cadence Virtuoso, FinFET, DRC LVS ERC
This role has been open 30 days — well above the 14-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
30
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Median days open
14 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (30 roles · 19 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 30 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 30 d | 14 d (+16 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: analog layout, mixed-signal ASIC, Cadence Virtuoso, FinFET, DRC LVS ERC
Who's hiring in this category
- Celero · 4 open roles · median 1 d
- Infineon Technologies · 3 open roles · median 29 d
- QORVO · 3 open roles · median 13 d
- Marvell Technology · 2 open roles · median 5 d
- Monolithic Power Systems · 2 open roles · median 15 d
- onsemi · 2 open roles · median 15 d
How we counted: 30 open Analog IC Design (Analog Layout) roles from 19 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.