Semiconductor Principal Design Engineer - Tokyo, Japan
Originally posted 21 July 2026 by the employer — open 51 days.
About the role
This Principal Design Engineer contributes to the design, layout, and optimization of datapath circuits for NAND flash memory.
What you'll do
- Design and optimize TSV interface circuits connecting memory die to logic die, including Rx/Tx circuits.
- Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis.
- Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface.
- Develop clocking and synchronization strategies for the highly parallel internal bus, including wave pipeline design and clock distribution.
- Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression.
- Support post-silicon validation, debug, and correlation activities, identifying schematic edits and driving tape-out revisions.
What you'll need
- BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND, or other high-density memory technologies.
- Experience with TSV interface circuit design or high-speed memory interface design (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity.
- Advanced knowledge and understanding of highly parallel bus performance, power, and area optimization, including clock distribution and skew management.
- Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams.
Nice to have
- Hands-on experience in utilizing AI to improve quality of design and efficiency.
- Experience on chip level PDN optimization.
- Comprehensive understanding on CMOS device and device reliability.
- Comprehensive understanding on CMOS BSIM model and CMOS target for high-speed IO operation.
- Experience with signal/power integrity, power delivery network design, physical design.
Skills: IO/datapath blocks, serializer, deserializer, clock distribution, high-speed IO circuit performance
This role has been open 155 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 115 d | 91 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: IO/datapath blocks, serializer, deserializer, clock distribution, high-speed IO circuit performance
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.