Semiconductor Layout & Tape-Out Engineer - Kodaira, Japan
Originally posted 6 October 2026 by the employer.
This role focuses on end-to-end tape-out execution for Gallium Nitride (GaN) technologies.
About the role
This role is responsible for end-to-end tape-out execution for Gallium Nitride (GaN) technologies. It supports multiple concurrent tape-out flows, ensuring accurate, high-quality mask data delivery.
What you'll do
- Perform and support PCM (Process Control Monitor) layout development and verification.
- Design and maintain alignment mark layouts in compliance with lithography and process requirements.
- Run Design Rule Checks (DRC) and mask data validation.
- Execute mask data generation workflows in accordance with foundry requirements.
- Perform mask data verification and signoff, ensuring format accuracy and rule compliance.
- Manage tape-out (TO) submissions and mask ordering processes.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or a related field.
- Familiarity with reticle design and mask data preparation flows.
- Basic understanding of mask data formats (e.g., MEBES/JobDeck).
- Proficiency in layout and verification tools such as Cadence and Calibre.
- Experience working in a Unix/Linux environment.
- Japanese language proficiency and good communication skills in English.
Nice to have
- Experience in foundry tape-out processes.
- Experience working in cross-functional, global engineering environments.
- LEDIT experience.
Skills: PCM layout, mask data preparation, tape-out, DRC, Cadence and Calibre
This role has been open 21 days — well below the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 704 |
| Open roles in the wider Physical Implementation family | 41 | 1507 · 111 employers |
| Median days open | 5 d | 70 d (−65 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: PCM layout, mask data preparation, tape-out, DRC, Cadence and Calibre
Who's hiring in this category
- Cadence Design Systems · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology · 45 open roles · median 55 d
- GlobalFoundries · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.