RTL2GDS, Product Engineering Architect - San Jose, United States
$154,000 - $286,000 USD yearly
Originally posted 11 May 2026 by the employer. Relisted by the employer on 28 August 2026.
Focus on place-and-route flow and PPA optimization at 7nm and below within Cadence's Digital and Signoff Group (DSG).
About the role
Cadence’s Digital and Signoff Group (DSG) is hiring an RTL2GDS Product Engineering Architect in San Jose. In this role, you will provide place-and-route expertise to Cadence customers and internal development teams to support the development of chip design software tools.
What you'll do
- Support Cadence digital products and collaborate with R&D, Application Engineering, and product marketing teams. - Track and resolve customer issues alongside R&D and release teams. - Conduct design benchmarks to assess tool performance and capabilities. - Develop flows and methodologies tailored to customer design needs across the RTL to GDSII flow. - Diagnose customer design challenges and deliver technical solutions for timing closure and PPA optimization.
What you'll need
- BS in Electrical Engineering with at least seven years of experience in digital implementation as either a design or product engineer. - Solid understanding of VLSI physical design and timing analysis, including clock tree synthesis, routing optimization, and silicon signoff challenges. - Hands-on experience with timing closure and PPA optimization at 7nm and below. - Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below nodes. - Thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow. - Proficiency in scripting languages or AI tools for productivity enhancement.
Skills: ASIC design methodologies, RTL to GDSII flow, timing closure, PPA optimization, VLSI physical design, timing analysis