RTL Power Optimization Engineer – New College Grad 2026
Originally posted 21 July 2026 by the employer.
About the role
This role focuses on pre-silicon RTL and gate-level power analysis and optimization for data center, gaming, automotive GPU, and networking chips. Engineers implement power reduction techniques and AI-based methodologies in collaboration with architecture, ASIC design, and physical design teams.
What you'll do
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools to improve product power efficiency.
- Apply artificial intelligence to deliver RTL and architecture power optimization solutions.
- Perform comparative power analysis to spot trends and anomalies, and debug power bugs with architects and RTL designers.
- Select and run workloads for power analysis, and prototype architectural features in Verilog.
- Develop and share best practices for pre-silicon power analysis.
What you'll need
- Pursuing or recently completed an MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design, and VLSI concepts (or equivalent experience).
- Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and low-power design patterns at the RTL level.
- Familiarity with RTL implementation of low-power techniques such as clock gating, operand isolation, power gating strategies, and multi-VT usage.
- Knowledge of backend flows including logic synthesis and place-and-route, and their post-layout power and timing trade-offs.
- Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent.
- Strong Python programming skills for building automation scripts, data pipelines, and AI/ML-driven analysis flows.
- Coursework or hands-on experience in Machine Learning and Artificial Intelligence applied to EDA or silicon power problems.
- Experience debugging RTL or gate-level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root causes.
More semiconductor jobs: NVIDIA jobs · RTL design jobs · California jobs
This role has been open 101 days — well above the 58-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1050
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1050 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 1050 |
| Open roles in the wider Digital Design & Verification family | 257 | 3354 · 114 employers |
| Median days open | 67 d | 58 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 67 d
- Synopsys · 87 open roles · median 44 d
- AMD · 81 open roles · median 45 d
- NXP Semiconductors · 44 open roles · median 99 d
- Analog Devices · 42 open roles · median 46 d
- Intel Corporation · 34 open roles · median 22 d
How we counted: 1050 open Digital/RTL Design (RTL Design) roles from 99 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.