RTL Design Tech Lead (ASIC/SoC)
$250,000 - $350,000 USD yearly
About the role
This role drives micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs from architecture through tapeout. It combines hands-on individual contributor design work with technical leadership across engineering teams.
What you'll do
- Own end-to-end RTL design for major subsystems or full-chip blocks and define micro-architecture aligned with PPA targets.
- Lead and mentor a team of RTL engineers while driving design reviews, coding standards, and best practices.
- Collaborate closely with Design Verification (DV), Physical Design (PD), and STA / Timing / DFT teams.
- Ensure RTL quality through Lint, CDC, RDC checks, and low-power (UPF) compliance.
- Debug complex issues across RTL simulation, Gate-Level Simulation (GLS), and silicon bring-up.
- Work with foundry and backend constraints including timing, congestion, and IR drop to drive execution toward tapeout.
What you'll need
- Bachelor’s or Master’s in Electrical / Computer Engineering.
- 10+ years of experience in ASIC/SoC RTL design.
- Expert-level proficiency in SystemVerilog / Verilog RTL coding and micro-architecture design.
- Strong understanding of timing (setup/hold, STA correlation), CDC/RDC methodologies, reset strategies, clocking architectures, and low-power design (UPF/CPF).
- Proven experience leading blocks through multiple tapeouts and hands-on experience with synthesis tools such as Design Compiler.
- Experience with silicon bring-up and operating under tight tapeout schedules.
Nice to have
- Experience in advanced nodes such as 12FFC, 7nm, or 5nm.
- GLS expertise including SDF, X-propagation, and power-aware simulations.
- Knowledge of DFT including scan, MBIST, and compression.
- Experience with high-speed IPs such as DDR, PCIe, SerDes, or memory subsystems.
- Scripting proficiency in Python or Tcl.
- Prior collaboration with foundries such as TSMC, or exposure to packaging including flip-chip, bump planning, and IO constraints.
Skills: RTL design, micro-architecture, SystemVerilog, Verilog, PPA, tapeout
More semiconductor jobs: RTL design jobs · Sunnyvale jobs
This role has been open 199 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Bolt Graphics | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1096 |
| Open roles in the wider Digital Design & Verification family | 16 | 3525 · 120 employers |
| Median days open | 141 d | 64 d (+77 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: RTL design, micro-architecture, SystemVerilog, Verilog, PPA, tapeout
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.