Senior RTL Design / Microarchitecture Engineer
$160,000 - $220,000 USD yearly
About the role
As a Senior RTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of SoC/IP designs. You will collaborate with architecture, verification, and physical design teams on performance, power, and area optimizations.
What you'll do
- Define and develop microarchitecture specifications from high-level architecture requirements.
- Design and implement RTL in SystemVerilog and Verilog for complex digital blocks.
- Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level.
- Collaborate with verification teams to ensure coverage and design correctness, and debug issues across simulation, GLS, and silicon bring-up.
- Support IP integration into SoC-level environments and work with physical design teams on timing closure, synthesis constraints, and floorplan-aware design.
- Participate in design reviews, architecture discussions, design documentation, and methodology improvements.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or a related field.
- 7–12 years of experience in RTL design and microarchitecture.
- Expertise in RTL design using SystemVerilog/Verilog, microarchitecture development, performance optimization, and pipelining techniques.
- Experience with simulation and debugging tools such as Synopsys VCS or Cadence Xcelium.
- Familiarity with synthesis and timing concepts, including Synopsys Design Compiler.
- Strong understanding of digital design fundamentals, including FSMs, pipelines, caches, and memory interfaces within ASIC/SoC environments.
Nice to have
- Domain experience in CPU, GPU, AI/ML accelerators, networking, or high-speed data processing.
- Knowledge of memory subsystem design, including SRAM, cache hierarchies, and coherency.
- Familiarity with low-power design techniques such as clock gating and power domains.
- Exposure to formal verification or linting tools, as well as GLS, SDF annotation, and silicon debug.
- Scripting skills in Python or TCL for automation, and understanding of hardware-software interaction including firmware and drivers.
Skills: RTL design, SystemVerilog, Verilog, microarchitecture, PPA optimization
More semiconductor jobs: RTL design jobs · Sunnyvale jobs
This role has been open 199 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Bolt Graphics | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1096 |
| Open roles in the wider Digital Design & Verification family | 16 | 3525 · 120 employers |
| Median days open | 141 d | 64 d (+77 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: RTL design, SystemVerilog, Verilog, microarchitecture, PPA optimization
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.