RFIC Layout Engineer - Austin, United States
Originally posted 27 October 2026 by the employer.
About the role
As an RFIC Layout Engineer on the Wireless SoC Radio Team, you will deliver custom layouts for CMOS radio transceivers into high-volume production in advanced CMOS technology nodes. The scope covers RF, analog, and mixed-signal blocks ranging from RF front-end amplifiers to data converters, baseband filters, phase-locked loops, crystal oscillators, and band gap references.
What you'll do
- Implement custom RF, analog, and mixed-signal layouts for highly integrated CMOS wireless transceivers. - Execute layout techniques for device matching, parasitic minimization, RF shielding, and high-frequency routing. - Address physical layout challenges including RC delay, electromigration, and signal coupling across advanced nodes. - Manage advanced process effects including LOD, WPE, DNW, PN junctions, and guard rings. - Run and interpret physical verification checks including DRC, ERC, and LVS using Calibre in FinFET technologies.
What you'll need
- BS and 10+ years of relevant industry experience. - Hands-on layout experience in FinFET technologies.
Nice to have
- Experience in custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge. - High level proficiency in interpretation of CALIBRE DRC, ERC, and LVS in FinFET Technology. - Knowledge of Cadence layout tools. - Scripting skills in PERL or SKILL.
Skills: RF layout, FinFET, Calibre DRC, LVS, Cadence, transceiver