About the role
Apple is seeking an RF/Analog/Mixed Signal Engineer in Austin, Texas to design complex analog and mixed-signal circuits at the transistor level for high-speed, low-power communication systems. The role focuses on clock distribution, CDR, duty cycle correctors, phase interpolators, and reference clock receivers.
What you'll do
- Define and document functional and performance requirements for block- and chip-level specifications aligned with system-level goals.
- Design complex analog and mixed-signal circuits at the transistor level using Virtuoso to satisfy power, performance, and area constraints.
- Conduct block-level simulations and analyses to verify circuit functionality and performance across environmental conditions.
- Design clock distribution networks, CDR circuits, Duty Cycle Correctors (DCC), and Phase Interpolators (PI) to optimize clock quality and reduce power draw.
- Design a 100MHz reference clock receiver with 50-ohm termination to deliver clocks to the PLL with minimal jitter contribution.
- Perform environment testing and reliability analysis across process, voltage, and temperature (PVT) conditions.
What you'll need
- Master's Degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
- Experience designing and analyzing high-speed analog and mixed-signal building blocks including PLL, LDO, ADC, DAC, and Phase-Interpolator.
- Experience with end-to-end SERDES systems including TX/RX design, channel characteristics, and equalization techniques.
- Experience utilizing RTL/Verilog modeling to develop models for mixed-signal blocks for system-level design verification.
- Experience modeling in MATLAB for SERDES performance analysis, including jitter tolerance and equalization analysis.
- Experience with testing equipment including spectrum analyzers, oscilloscopes, and signal generators for post-silicon validation and testing.
- Proficiency in layout techniques for analog and high-speed circuits, including matching and noise minimization.
- Experience using Python and Shell scripting for simulation automation and data analysis, alongside design validation tools including EMIR, static timing analysis, and DFT.
Skills: SERDES, CDR, PLL, Phase Interpolator, Virtuoso, Duty Cycle Corrector
More semiconductor jobs: Apple jobs · Signal integrity jobs
This role has been open 0 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
249
|
Median days open
78 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (249 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 249 |
| Open roles in the wider Analog & Mixed-Signal family | 67 | 1528 · 111 employers |
| Median days open | 9 d | 78 d (−69 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Skills observed across this category: SERDES, CDR, PLL, Phase Interpolator, Virtuoso, Duty Cycle Corrector
Who's hiring in this category
- Synopsys · 34 open roles · median 39 d
- AMD · 24 open roles · median 45 d
- Cadence Design Systems · 21 open roles · median 149 d
- Qualcomm · 17 open roles · median 83 d
- NVIDIA · 16 open roles · median 210 d
- Micron Technology · 10 open roles · median 49 d
How we counted: 249 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 50 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.