R&D Packaging and Signal Integrity Intern - US-CO-Col Springs-Bldg C, United States
$35 - $39 USD yearly
Originally posted 8 September 2026 by the employer — open 12 days.
About the role
As an R&D Packaging and Signal Integrity Intern, you will design, optimize, and implement ASIC packaging and subsystem solutions.
What you'll do
- Design, optimize, and implement ASIC packaging and subsystem solutions that meet product functionality, performance, quality, and schedule requirements.
- Perform ASIC package, module, and subsystem development, including layout, integration, SI/PI analysis, and power delivery network design.
- Model and optimize high-frequency RF and high-speed digital I/O interconnects.
- Collaborate with system, IC design, and test teams to develop and define hardware architecture, requirements, functionality, and performance.
- Collaborate with test and reliability teams in the characterization and qualification of each ASIC.
- Provide lifecycle support for existing ASIC components.
What you'll need
- Working towards a BS, MS, or PhD degree in Electrical, Mechanical, or Materials Engineering or equivalent.
- CAD Modeling and/or Simulation coursework and in-school experience.
- Understanding of Electrical Engineering and RF signal integrity principles.
Nice to have
- Signal integrity analysis using commercially available tools.
- Package or PCB layout experience using commercially available tools.
- Classroom or work experience in hardware/circuit design, RF/microwave design, high-frequency modeling/optimization, or high-power density design.
- Experience with semiconductor, packaging, and printed circuit board technologies, associated materials, manufacturing processes, and design methodologies.
- Knowledge of thermodynamics and thermostructural analysis principles.
- Understanding of materials science principles.
- Familiarity with IC design methodologies, processes, and workflows.
Skills: ASIC packaging, SI/PI analysis, power delivery network, high-frequency RF, high-speed digital I/O interconnects
This role has been open 12 days — well below the 38-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
67
|
Median days open
38 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (67 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 67 |
| Median days open | 96 d | 38 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC packaging, SI/PI analysis, power delivery network, high-frequency RF, high-speed digital I/O interconnects
Who's hiring in this category
- Micron Technology · 13 open roles · median 143 d
- AMD · 6 open roles · median 27 d
- Marvell Technology · 6 open roles · median 13 d
- Broadcom · 5 open roles · median 163 d
- NVIDIA · 5 open roles · median 38 d
- Amazon · 4 open roles · median 26 d
How we counted: 67 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.