Product Quality Engineer - San Jose, United States
Originally posted 27 May 2026 by the employer.
About the role
The Product Quality Engineer ensures robust quality systems across suppliers, domestic contract manufacturing, and integration partners (L10 server, L11 rack). The role owns quality assurance across semiconductor (ASIC/chip), PCB/A, and rack integration hardware builds.
What you'll do
- Lead quality assurance across semiconductor (ASIC/chip), PCB/A, L6 component suppliers, L10 server manufacturers, and L11 rack integration partners. - Establish and maintain IQC, IPQC, and OQC processes, including inspection criteria, control plans, and quality gates across incoming materials, PCB/A manufacturing, system assembly, and rack integration. - Partner with suppliers and contract manufacturers to oversee SMT processes, including SPI, AOI, and X-ray inspection. - Collaborate with Test Engineering to define system-level test coverage, burn-in protocols, reliability validation, and production acceptance criteria. - Drive failure analysis, root-cause investigations, and structured corrective and preventive actions using 8D, CAPA, and FMEA methodologies. - Track, analyze, and report quality metrics including yield, Cpk/SPC, defect density, escapes, and DPPM.
What you'll need
- 5+ years of experience in quality engineering, supplier quality, or manufacturing quality supporting ASIC/chip, semiconductor, PCB/A, server, or high-performance hardware products. - Hands-on experience supporting quality across L6 components, L10 server assembly, and L11 rack integration with Tier 1 contract manufacturers or ODMs. - Working knowledge of PCB/A manufacturing processes, including SMT, SPI, AOI, and X-ray inspection. - Demonstrated experience establishing and managing IQC, IPQC, and OQC quality systems in high-volume manufacturing environments. - Working knowledge of structured quality methodologies including 8D, CAPA, FMEA, SPC, Cpk, and control plans. - Experience tracking and improving manufacturing quality metrics such as yield, DPPM, defect density, and production escapes.
Nice to have
- Background in AI ASIC or high-performance compute hardware. - Experience with L11 rack-level integration and validation. - Exposure to thermal/power stress testing and system reliability engineering. - Prior experience ramping high-complexity systems from NPI into mass production. - Engineering background in electrical, mechanical, manufacturing, or industrial engineering. - Experience developing supplier quality strategies for advanced compute hardware programs.
Skills: quality assurance, incoming, in-process, outgoing inspection, burn-in protocols, failure analysis, root-cause investigations, quality metrics (yield, defect density)
This role has been open 149 days — well above the 61-day median for Product Engineering roles.
Product Engineering · Reliability Engineering
|
Open roles in category
66
|
Median days open
61 d
|
Median salary
$138k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (66 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 66 |
| Open roles in the wider Silicon Validation & Test family | 10 | 2238 · 112 employers |
| Median days open | 149 d | 61 d (+88 d vs this employer) |
| Median salary (USD postings) | — | $138k |
Skills observed across this category: quality assurance, incoming, in-process, outgoing inspection, burn-in protocols, failure analysis, root-cause investigations, quality metrics (yield, defect density)
Who's hiring in this category
- Micron Technology · 13 open roles · median 171 d
- Analog Devices · 8 open roles · median 42 d
- onsemi · 5 open roles · median 17 d
- Qualcomm · 4 open roles · median 108 d
- Texas Instruments · 4 open roles · median 63 d
- Applied Materials · 3 open roles · median 24 d
How we counted: 66 open Product Engineering (Reliability Engineering) roles from 25 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.