Process Engineer – Semiconductor Heterogeneous Integration - US-CA-Santa Rosa-Bldg 2, United States
$126,930 USD yearly
Originally posted 13 January 2026 by the employer. Relisted by the employer on 28 July 2026.
This role focuses on design enablement and advanced packaging architecture for microwave and mmWave System-in-Package (SiP) modules.
About the role
This role emphasizes design enablement and advanced packaging architecture for System-in-Package (SiP) modules integrated with microwave and mmWave subsystems. It focuses on heterogeneous integration to combine diverse semiconductor technologies into high-performance packaging solutions.
What you'll do
- Collaborate with upstream design teams to define packaging architectures and integration strategies. - Develop design rules and guidelines for manufacturability and reliability. - Evaluate new materials, interconnect technologies, and advanced packaging concepts. - Perform feasibility studies and risk assessments for new designs. - Partner with process and integration engineering and manufacturing teams to ensure smooth technology transfer. - Support prototype builds and analyze performance data to refine design approaches.
What you'll need
- B.S., M.S., or Ph.D. in Materials Science, Mechanical Engineering, Chemical Engineering, Electrical Engineering, or a related field. - 3+ years of applicable semiconductor manufacturing industry experience (internship, lab work, or research experience considered). - Local residency or willingness to relocate to Santa Rosa, CA. - Status as a U.S. person under U.S. export control laws and regulations (8 U.S.C. 1324b(a)(3)).
Nice to have
- Experience in semiconductor packaging design and integration. - Expertise in design for manufacturing and reliability. - Background in advanced interconnect technologies, including flip-chip and thermocompression bonding. - Expertise in materials science for packaging applications. - Experience with statistical analysis and design of experiments (DOE). - Familiarity with System-in-Package (SiP), SMT, and heterogeneous integration.
Skills: design enablement, advanced packaging architecture, System-in-Package (SiP), heterogeneous integration, packaging architectures
This role has been open 216 days — well above the 49-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
49 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (69 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 69 |
| Median days open | 132 d | 49 d (+83 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: design enablement, advanced packaging architecture, System-in-Package (SiP), heterogeneous integration, packaging architectures
Who's hiring in this category
- AMD · 10 open roles · median 33 d
- Micron Technology · 9 open roles · median 178 d
- Marvell Technology · 6 open roles · median 23 d
- NVIDIA · 6 open roles · median 48 d
- Broadcom · 4 open roles · median 148 d
- GlobalFoundries · 4 open roles · median 116 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.