Process Engineer - Batu Kawan, my, Malaysia
Originally posted 15 September 2026 by the employer — open 4 days.
About the role
This role is responsible for the Underfill (UF) process for flip-chip die-level assembly, supporting process and equipment solutions to meet quality, development, and operational requirements.
What you'll do
- Be responsible for the Underfill (UF) process for flip-chip die-level assembly.
- Maintain assembly yield and assembly test yield related to the Underfill process.
- Set up new Underfill processes, materials, and recipes, including process window studies and DOE execution.
- Perform root cause analysis and problem-solving using methodologies such as 5M+1E, 5 Whys, DMAIC, and 8D.
- Monitor and optimize Underfill equipment performance, including preventive maintenance coordination and troubleshooting.
- Develop and maintain process documentation, including work instructions, process specifications, and technical reports.
What you'll need
- Bachelor's Degree or higher in Engineering (Electrical, Mechanical, Physics, Materials Science, or a related field).
- Minimum 4–5 years of experience in semiconductor assembly process engineering.
- Experience in Underfill process development and sustaining.
- Strong knowledge of semiconductor assembly processes and flip-chip die-level assembly technology.
- Working knowledge of Failure Mode and Effects Analysis (FMEA), Statistical Process Control (SPC), 8D Problem Solving, Six Sigma methodologies, Design of Experiments (DOE), and statistical analysis tools such as Minitab and JMP.
Nice to have
- Familiarity with Nordson dispenser, Heller reflow oven, and C-Scan equipment.
- Knowledge of underfill defect mechanisms such as voiding, fillet irregularities, incomplete fill, delamination, overflow, and package warpage.
- Experience supporting New Product Introduction (NPI), high volume manufacturing (HVM), process transfer, and manufacturing ramp-up activities.
- Familiarity with reliability qualification requirements, including MSL, TCT, HTS, HAST, and board-level reliability testing.
- Familiarity with SEM, SAM (C-Scan), X-ray, and cross-section analysis for failure investigation and process validation.
This role has been open 4 days — well below the 53-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
299
|
Median days open
53 d
|
Median salary
$179k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (299 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 299 |
| Open roles in the wider Process, Fab & Equipment family | 74 | 9328 · 108 employers |
| Median days open | 18 d | 53 d (−35 d vs this employer) |
| Median salary (USD postings) | — | $179k |
Who's hiring in this category
- KLA Corporation · 49 open roles · median 100 d
- Micron Technology · 36 open roles · median 27 d
- Renesas Electronics · 21 open roles · median 19 d
- Infineon Technologies · 18 open roles · median 39 d
- Intel Corporation · 13 open roles · median 74 d
- Lumilens · 13 open roles · median 43 d
How we counted: 299 open Packaging Engineering (Advanced Packaging) roles from 58 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.